Testing complementary pass-transistor logic circuits

Abstruct Behavior of basic and complex logic gates using complementary pass-transistor logic (CPL) under various single-stuck faults are investigated. The result shows that all stuck-on faults in the basic CPL gates can be detected by current monitoring, but no logic monitoring is possible. Similarly all bridging faults between gate and source of basic CPL gates can be detected only by current monitoring. However, for bridging faults between gate and drain of basic CPL gates, it is shown that all faults can be detected by current monitoring, except for the MOS devices having same input variable at the gate and the drain terminal. All stuck-open fault in the basic CPL gates are detectable by logic monitoring using appropriate two-pattern test. Testability analysis of CPL full adder under single stuckon fault shows that stuck-on fault on all the MOS transistors of the SUM logic and the CARRY logic circuit can be detected by signal source current monitoring with appropriate test vectors. For some of these test vectors the fault can also be detected by logic monitoring, but in all cases this is also accompanied by a large flow of signal source current. Finally it is concluded that current monitoring (IDDQ testing ) is the best method for fault detection in CPL circuits and gives a very wide range of fault coverage.